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VERILOG CODE FOR HALF ADDER WITH TEST BENCH

• VERILOG CODE FOR HALF ADDER WITH TEST BENCH, TECHNOLOGY SCHEMATIC

Half Adder is a combinational circuit which are used to add any 2 binary numbers and generate two results.

1. SUM
2. CARRY

SUM is generated by XOR operation of two input Signals, whereas CARRY is generated by AND operation between two input Signals.

Half Adder is basic building block for other high level ADDERS which are more faster, complex in nature.

The circuit diagram for implementation of Half Adder using Logic Gates is shown below:

• VERILOG CODE FOR HALF ADDER

module ha(a, b, sum, carry);

// save file with ha.v extension 

input a;

input b;

output sum;

output carry;

assign carry=a&b;                           

assign sum=a^b;                             

endmodule

• VERILOG TESTBENCH FOR HALF ADDER

module halfaddert_b;

// save file with  halfaddert_b.v extension

reg a,b;

wire sum,carry;

ha m1 (a,b,sum,carry);

initial begin

$monitor ($time, ,"a=%b,b=%b,sum=%b,carry=%b",a,b,sum,carry);

a = 0; b = 0;

#10 b = 1;

#10 a = 1;

#10 b = 0;

end

endmodule

• SIMULATION OF HALF ADDER (VERILOG APPROACH)

After compiling both codes, the simulation results can be viewed as under, 

The truth table inset within the simulation results would be helpful for  understanding picture more clearly.

• SYNTHESIS OF HALF ADDER (VERILOG APPROACH)

After simulation, next step would be generation of synthesis logic schematic and technology schematic.

The working of  Half Adder can be decided by Technology schematic (LUT - Look Up Table)

The Snap-Shots of Technology Schematic and 2 LUTs for Half Adder (Verilog Approach) is shown below 

Note: Look-up tables (LUTs) are used to implement function generators in CLBs.

 An n-bit LUT can encode any n-input Boolean function by modeling such functions as truth tables. This is an efficient way of encoding Boolean logic functions, and LUTs with 4-6 bits of input are in fact the key component of modern field-programmable gate arrays (FPGAs).

VERILOG CODE FOR D FLIP FLOP WITH TEST BENCH

• VERILOG CODE FOR D FLIP FLOP WITH TEST BENCH

The verilog code below shows the implementation of D Flip Flop. The Truth Table will help to understand the logic

For sake of simplicity we are not considering the SET & RESET Signals for implementing Verilog Code of D Flip Flop

• VERILOG CODE FOR IMPLEMENTATION OF D FLIP FLOP

module dffnew(d,clk,q);

input d, clk;

output reg q;

always @(posedge clk)

q <= d;

endmodule

• VERILOG TEST BENCH FOR D FLIP FLOP

module dfftstbnch;

reg d, clk;

wire q;

dffnew d1 (d,clk,q);

//Always at rising edge of clock display the signals

initial

begin

clk=0;

d = 0;

$monitor($time, ,"d=%b",d, ,"c=%b",clk, ,"q=%b",q);

end

 always #5 clk = ~clk;

 always #10      d = ~d;

initial #50 $finish;

endmodule

• OUTPUT FOR VERILOG CODE FOR D FLIP FLOP

• TECHNOLOGY SCHEMATIC FOR D FLIP FLOP VERILOG IMPLEMENTATION

• SIMULATION RESULTS FOR D FLIP FLOP IMPLEMENTED IN VERILOG FASHION

Chapter 1 Review Questions of 

Operating System by William Stallings

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Operating System William Stallings Solution First Chapter