VERILOG CODE FOR D FLIP FLOP WITH TEST BENCH

• VERILOG CODE FOR D FLIP FLOP WITH TEST BENCH

The verilog code below shows the implementation of D Flip Flop. The Truth Table will help to understand the logic

For sake of simplicity we are not considering the SET & RESET Signals for implementing Verilog Code of D Flip Flop

• VERILOG CODE FOR IMPLEMENTATION OF D FLIP FLOP

module dffnew(d,clk,q);

input d, clk;

output reg q;

always @(posedge clk)

q <= d;

endmodule

• VERILOG TEST BENCH FOR D FLIP FLOP

module dfftstbnch;

reg d, clk;

wire q;

dffnew d1 (d,clk,q);

//Always at rising edge of clock display the signals

initial

begin

clk=0;

d = 0;

$monitor($time, ,"d=%b",d, ,"c=%b",clk, ,"q=%b",q);

end

 always #5 clk = ~clk;

 always #10      d = ~d;

initial #50 $finish;

endmodule

• OUTPUT FOR VERILOG CODE FOR D FLIP FLOP

• TECHNOLOGY SCHEMATIC FOR D FLIP FLOP VERILOG IMPLEMENTATION

• SIMULATION RESULTS FOR D FLIP FLOP IMPLEMENTED IN VERILOG FASHION